In the field of semiconductor manufacturing, physical descriptions of microdevice layouts are generally represented using data formats such as GDSII. In this representation, individual circuit elements are represented by polygons, which are described as a sequence of vertices. For example, FIG. 1 shows a number of polygons 10, 12, 14, 16 while FIG. 2 shows the same polygons represented as a series of vertices. The elements of various physical layers in the device are represented by data layers in the description, and related groups of device elements on various layers can be combined in a description of a subset of the layout, often called a cell. In turn, cells can contain other, smaller cells, or be contained in larger cells, as illustrated in FIG. 3. The organization of cells (each of which can contain data for multiple layers) into a tree structure as shown in FIG. 3A is often called the hierarchy of the device.
It is clear that a hierarchical representation can represent an entire layout with greater compactness than a representation with no hierarchy, also called a flat representation. Products that import layout files for verification such as Calibre™ from Mentor Graphics Corporation, the assignee of the present invention, strive to retain as much of the original hierarchy as possible, and can in some cases reorganize the hierarchy or create additional levels of hierarchy for additional data compactness. An efficient hierarchical database can significantly reduce the size of the file required to describe the microdevice layout.
As the density of objects to be created in a semiconductor wafer increases, new technologies are required to print such objects. In particular, as the size and/or spacing between objects becomes smaller than the wavelength of light used for photolithographic patterning, a variety of optical distortions occur. In order to insure the microdevice is reliably manufactured, several resolution enhancement techniques (RETs) have been developed and are finding increasing adoption. These include: off-axis illumination techniques, such as annular, dipole, and quadrupole illumination; phase-shifting mask techniques, including both attenuated and alternating or Levenson approaches, and OPC (Optical and Process Correction), in which the size and shape of the elements of the layout are corrected to produce an improved image.
To enable the adoption of these resolution enhancement techniques, the layout must be adapted to anticipate the optical effects that the imaging process will introduce. This requires software that will read and analyze the microdevice layout and alter the polygons accordingly. These alterations can take the form of changing sizes and shapes of polygons, moving polygons from one layer to another, creating additional polygons that assist printing fidelity, and even creating additional data layers for representing multiple phase regions on a single reticle or even multiple reticles used for multiple exposure techniques.
In these data manipulations for RET, and especially for those required for OPC, the decision about the necessary action requires an examination of the nearby features. Usually, “nearby” means within a specified “optical radius” that is related to the lithography wavelength, λ, and numerical aperture, NA, in which optical proximity effects will be significant. However, other definitions that incorporate other effects can be used as well.
Examining nearby features becomes more complex in a hierarchical database, since the nearby features in the layout may be in another cell of the hierarchy. Computations using polygons only within a cell may therefore ignore significant contributions from polygons in neighboring cells. Proper computation of the RET effects and layout manipulations must therefore look across cell boundaries, and up and down in the hierarchy as well.
The problem is most easily solved by flattening the database. With all polygons, and therefore all nearby polygons, on the same level of hierarchy, it is assured that all neighboring interactions will be accounted for. This flattening, however, makes a very large database representation for the microdevice, and destroys the many advantages that hierarchy brings.
To this end, the techniques of selective promotion can be used. In selective promotion for physical verification applications such as Design Rule Checking (DRC), various criteria are used to move only certain interacting polygons from a lower level of hierarchy to a higher one. This allows all the interacting features to be in the same level of hierarchy for computational purposes, while leaving the unrelated features in the lower level of hierarchy. These techniques generally work well, are quite efficient, and have been used extensively in physical verification products such as Calibre®. However, as usually implemented, selective promotion can force polygons that are only partly promoted to be cut. The introduction of these points of scission can be very awkward for many computations used to calculate RET effects.
There is therefore a need for a database management technique, such as selective promotion, that allows for a hierarchical representation of the microdevice, yet also allows accurate and efficient computations of RET effects and the necessary data manipulations.